The present invention relates to method of and apparatus for an operational processing using a binary number of a floating point representation according to the IEEE (Institute of Electrical and Electronics Engineers) Standard 754 or one which is conformed thereto.
With recent complication of scientific technical calculation or graphic procedure, there is an increased demand for a high-speed and accurate floating point operation. A computer is adapted to execute a processing using only limited digits of a floating point number. Accordingly, there often occur errors in a result obtained by a floating point operation. Operational precision considerably depends on the hardware arrangement of a computer, but by following the IEEE standard 754, errors resulting from the hardware arrangement can be prevented.
In the IEEE Std. 754, a format whose total bit number is 32 including a 1-bit sign S, an 8-bit exponent E and a 23-bit fraction F, is specified for a single-precision floating point binary number. Also, a format whose total bit number is 64 including a 1-bit sign S, an 11-bit exponent E and a 52-bit fraction F, is specified for a double-precision floating point binary number. Generally, there is used a floating point number for which normalization has been performed such that a virtual non-zero value bit and the radix point are located upper than the most significant bit (MSB) of the fraction F. However, a bias is given to an actual exponent such that the exponent E is a positive value. For single precision for example, there is used, as an exponent E, a value obtained by adding 127 as a bias to an actual exponent. That is, a real number R1 expressed as a normalized number of single precision is expressed as follows: EQU Rl=(-1).sup.S 2.sup.E-127 (1.F) (1)
wherein 1.F is a mantissa M.
In the IEEE Std. 754, it is defined that, when an operational result is a neighborhood value of 0, this is represented as a denormalized number. For single precision for example, the exponent E is made 0 and there is executed a denormalize processing to shift the fraction F such that the weight of the zero-value bit upper by one bit than the radix point is 2.sup.-126. In this case, a real value R2 expressed as a denormalized number is expressed as follows: EQU R2=(-1).sup.S 2.sup.-126 (0.F) (2)
wherein the mantissa M is 0.F.
There is a phenomenon that the number of digits of an effective numeral is greatly decreased when there are added two numerals of which absolute values are substantially the same and of which signs are different from each other. Such a phenomenon is called "cancelling". In subtraction of floating point numbers slightly different in value from each other, when an exponent of the minuend is equal to an exponent of the subtrahend, subtraction of their mantissas is executed without a digit position justifying operation. For example, when a mantissa of the minuend is 1.100101 . . . and a mantissa of the subtrahend is 1.100010 . . . , the result of subtraction of the mantissas is equal to 0.000011 . . . Thus, when the value of the bit upper by one bit than the radix point is 0 in the result of an operation, it is said that "cancelling of mantissa" has been generated. The number of zeros which are present continuously from the position of the bit upper by one bit than the radix point, is called an amount of cancelling of mantissa. In this example, the amount of cancelling of mantissa is 5.
A floating point number presenting such cancelling of mantissa, is normalized by executing, on a mantissa M, a left shift processing having a shift amount equal to the amount of cancelling and by correcting an exponent E such that the amount of cancelling is subtracted from the exponent E. In the following description, a left shift amount required at the time when cancelling of mantissa has been generated, will be expressed as an amount of cancelling LSA.
When the exponent E is not greater than the amount of cancelling of mantissa LSA and the amount of cancelling LSA is subtracted from the exponent E for normalization, the exponent after correction becomes not greater than 0. When an operational result cannot be expressed as a normalized number, the denormalize processing above-mentioned is then required.
The hardware of a conventional computer is adapted to execute a processing of a normalized number only. More specifically, when it is judged that a value obtained by executing a normalize processing on an operational result in a hardware, cannot be expressed as a normalized number, the normalize processing is interrupted as regarded that an exception has occurred, and a denormalize processing is then entrusted to the software. Accordingly, the denormalize processing is executed after the normalize processing has been executed. This presents the problem that a desired operational result cannot be obtained at a high speed.